Lead PSV Job Description
Responsibilities:
As a creative engineer with a demonstrated knowledge of SoC (System On Chip) Validation containing multi core CPU/GPU subsystems as well as high speed interfaces like PCIe, DDR , USB etc,
you will be owning validation of IP/ complex subsystems in systems’ environment and developing robust validation methodology for subsystems/solutions.
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Required Skills and Experience :
• 8+ Yrs of Experience in Post Silicon Validation (for SoC)
• You will need experience of silicon validation for multiple sophisticated SoCs /ASICs containing multi core CPU/GPU subsystems as well as high speed interfaces like PCIe, DDR, USB etc.
• Your ability to make trade-offs between power, performance and area will be vital
• You possess the expertise knowledge of developing Validation test content using C, C++ etc.
• Exposure to all stages of Silicon Validation will be crucial, including use-case validation.
• Exposure to producing validation specifications and documentation describing sophisticated designs.
• Have expert knowledge in computer architectures and systems.
• Practical experience of working on Processor based system designs
• Knowledge of shell programming/scripting (e.g. Tcl Perl, Python etc.)
• Deeper Understanding of High speed peripheral controller validation like PCIe / DDR / USB etc.
Debugging Tools –
- Oscilloscope (Keysight InfiniiVision, Tektronix MDO3000 series) ,
- Logic Analyser (Tektronix TLA series, Agilent 16900 series) ,
- In Circuit Emulator JTAG (Lauterbach TRACE32, ARM DSTREAM, Xilinx ChipScope),
- PCIE /USB Protocol Analayser (LeCroy PCIe Analyzer, Teledyne LeCroy USB Protocol Analyzer)
“Nice To Have” Skills and Experience :
• Deeper understanding of CPU/ GPU/ Media subsystem in SoC environment and proven expertise in owning validation requirements & Validation Plan.
• Hands on Experience in validating multiple sub systems for ASICs/ SoCs in system environment ( across Emulation, FPGA and Development/Eval board), owning all phases of validation ( Test development, Execution and Debug) for owned sub systems.
• Understanding of SoC security aspects